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An overview of the I C module is shown in Figure 15.1 (p. 145) .
Figure 15.1. I C Overview
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15.3 Functional Description
2
2
Peripheral Bus
I 2 C Control and
Status
Transm it Buffer
Receive Buffer
I2Cn_SDA
Sym bol
Generator
Transm it
Shift Register
Receive
Shift Register
Pin
ctrl
I2Cn_SCL
Receive
Controller
Clock generator
15.3.1 I C-Bus Overview
The I C-bus uses two wires for communication; a serial data line (SDA) and a serial clock line (SCL) as
Figure 15.2. I C-Bus Example
Address
Recognizer
2
2
show in Figure 15.2 (p. 145) . As a true multi-master bus it includes collision detection and arbitration
to resolve situations where multiple masters transmit data at the same time without data loss.
2
V DD
I 2 C m aster
#1
I 2 C m aster
#2
I 2 C slave
#1
I 2 C slave
#2
I 2 C slave
#3
R p
Each device on the bus is addressable by a unique address, and an I C master can address all the
I C Pull-up Resistor Equation
SDA
SCL
2
devices on the bus, including other masters.
Both the bus lines are open-drain. The maximum value of the pull-up resistor can be calculated as a
function of the maximal rise-time tr for the given bus speed, and the estimated bus capacitance Cb as
shown in Equation 15.1 (p. 145) .
2
Rp(max) = tr/0.8473 x Cb
(15.1)
The maximal rise times for 100 kHz, 400 kHz and 1 MHz I C are 1 μs, 300 ns and 120 ns respectively.
2
Note
The GPIO drive strength can be used to control slew rate.
2011-04-12 - d0001_Rev1.10
145
www.energymicro.com
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